Method for manufacturing semiconductor device

ABSTRACT

The present invention is provided to manufacture a semiconductor device capable of polishing evenly and separating the adjacent word lines by performing the flattening process using slurry with a doping material added during the polishing process.

BACKGROUND

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for manufacturing asemiconductor device, and, more specifically, to a method formanufacturing a semiconductor device capable of securing the stabilityin a polishing process for forming a landing plug.

[0003] 2. Discussion of Related Art

[0004] Generally, a polishing process is performed for an electricisolation of word lines at the time of manufacturing a semiconductor.However, after the polishing process, an insulator film is over-disheddue to differences of an etching rate between the insulator filmdeposited for insulating of the word lines and a poly silicon film for alanding plug (hereinafter also referred to as a “LP”). Thereby, slurryresidues generated during the polishing process become to remain on anupper face of the insulator film over-dished. The aforementioned slurryresidues are mostly composed of metal materials having electricconductivity, and they come to remain as they are because it isdifficult to remove them through the following cleaning process. Theresidues, as described above, affect the electric separation of wordlines, seriously.

[0005] The latest technologies decrease the polishing amount on theprocess to during the polishing process. However, in such a case, thereare many problems in the electric separation of word lines, relatively.The reason is that the word lines of regions to be opened on forming alanding plug contact for LP are more attacked relatively than the otherregions not to be opened, whereby the profile of upper word lineschanges into a round shape. Therefore, the upper area of LP becomes tobe larger and the electric separation margin of word lines gets moredeteriorated. Though the polishing amount is increased again at the timeof the polishing process to overcome these problems, the residualnitride film of word lines becomes to decrease, whereby the process offorming storage nodes and bit line self align contacts is affected and,furthermore, the short between these and tungsten silicide of word linewould be generated.

SUMMARY OF THE INVENTION

[0006] The present invention is directed to a method for manufacturing asemiconductor device capable of securing the stability of a polishingprocess for forming a landing plug and the electric separation of wordlines stably.

[0007] According to a preferred embodiment of the present invention,there is provided a method for preventing the short from taking place byimproving the marginality of space when forming storage nodes or bitline self align contacts, wherein the short otherwise could be generatedbetween storage nodes or bit line self align contacts and word lines.

[0008] One aspect of the present invention is to provide a method formanufacturing a semiconductor device comprising the steps of: preparinga semiconductor substrate defined as an active region and a fieldregion; forming a number of word lines in the active region and thefield region of the semiconductor substrate; depositing an insulatorfilm over the upper part of a structure to insulate word lines;patterning the insulator film to open word lines of the active regionwhereby forming a landing plug contact; depositing a poly silicon filmto fill up the landing plug contact; performing a first polishingprocess using slurry including a first doping material and flatteningthe poly silicon film only, whereby exposing the insulator film; andforming a landing plug by performing a second polishing process usingslurry including a second doping material and by flattening all theupper part of the structure.

[0009] In the aforementioned of a method for manufacturing asemiconductor device according to another embodiment of the presentinvention, the first doping material is preferably boron and, theconcentration of said boron is preferably in the range of 2 wt % to 5 wt%.

[0010] In the aforementioned of a method for manufacturing asemiconductor device according to another embodiment of the presentinvention, the second doping material is preferably phosphorus and, theconcentration of said phosphorus is preferably in the range of 2 wt % to5 wt %.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIGS. 1 to 7 are cross-sectional views showing a semiconductordevice for explaining a method for manufacturing a semiconductor deviceaccording to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0012] Now the preferred embodiments according to the present inventionwill be described with reference to the accompanying drawings. Sincepreferred embodiments are provided for the purpose that the ordinaryskilled in the art are able to understand the present invention, theymay be modified in various manners and the scope of the presentinvention is not limited by the preferred embodiments described later.

[0013] Referring to FIG. 1, a semiconductor substrate 102 is provided,wherein the semiconductor substrate is defined as an active region and afield region and it is cleaned by the cleaning process using at leastone of diluted HF (DHF), SC-1, and BOE. A field oxide film 104 is formedin the field region of the semiconductor substrate 102. The field oxidefilm 104 is formed to have a trench structure using shallow trenchisolation (STI) process or LOCal oxidation of silicon (LOCOS) process.

[0014] Referring to FIG. 2, a number of gate electrodes 112(hereinafter, “word lines”) are formed on the semiconductor substrate102 including the active region and the field region, which is the fieldoxide film 104. Word lines 112 include the gate oxide film 106, the gatelayer 108, and a hard mask layer 110. The gate layer 108 includes atleast one of the poly silicon films or of the doped poly silicon films,or is formed to have the structure including poly silicon films and atleast one of the insulator films between poly silicon films. The hardmask layer 110 is formed with the nitride film.

[0015] Subsequently, source and drain junction areas composed of low andhigh-density junction areas are formed on the semiconductor substrate,which is exposed to the both sides of word lines 112 in the activeregion and the field region. The low density junction area is formed bythe lightly drain doped (LDD) ion-planting process. The high-densityjunction area is formed by the high density ion planting process using amask as a spacer 114, wherein the spacer is formed in the both sides ofword lines 112. On the other hand, the spacer 114 is formed with thenitride film thereof, or the stacked structure of the oxide film and thenitride film.

[0016] Referring to FIG. 3, the insulator film 116 is deposited over theupper part of the structure. The insulator film 116 separates word lineselectrically which are formed adjacently in the active region and thefield region. The insulator film 116 is formed using at least one of thegroup comprising spin on glass (SOG), un-doped silicate glass (USG),boron-phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG),plasma enhanced tetra ethyl ortho silicate glass (PETEOS), and interpoly oxide (IPO). In addition, the insulator film 116 is deposited tofill the gap between word lines formed adjacently.

[0017] Referring to FIG. 4, a photoresist film is applied over the upperpart of the structure, and then the photoresist pattern (not shown)opened locally is formed by performing exposure and development processusing the photo mask, sequentially. It is preferable that thephotoresist pattern is formed such that the active region is opened. Inthe following, the insulator film 116 is etched by the process using anetching mask as a photoresist pattern, resulting in landing plug contact(LPC) 118 formed. At this time, the etching process for forming LPC 118is performed by a dry etching process requiring cheaper etching cost,however, preferably a plasma dry etching process.

[0018] Referring to FIG. 5, the photoresist pattern used as the etchingmask in FIG. 4 is removed through strip process. And then, the polysilicon film 120 for LP is deposited over the upper part of thestructure to fill LPC 118. At this moment, it is preferable that thepoly silicon film 120 for LP is deposited, thereby filling the gapbetween word lines formed in an LPC 118 region.

[0019] Referring to FIG. 6, the poly silicon film 120 for LP isflattened by performing a polishing process (hereinafter also referredto as “a 1^(st) polishing process”) of chemical mechanical polishing(CMP) method over the upper part of the structure. In the 1^(st)polishing process, doping material for flattening the poly silicon filmfor LP 120 only is silica-based slurry with boron (B) added, forexample. It is preferable that the concentration of B is in the range of2 wt % to 5 wt %. In the 1^(st) polishing process, for example, it ispossible that the pressure applied to the Main brain/Retain ring/Innertube (M/R/I) of CMP equipment is in the range of 2 to 8 psi (pound/in²),and P/H's rotation power of CMP equipment is in the range of 30 to 150rpm.

[0020] Referring to FIG. 7, a 2^(nd) polishing process is performed overthe upper part of the structure. In the above 2^(nd) polishing process,for example, the slurry with phosphorus (P) added is used as a dopingmaterial for flattening the insulator film 116, the poly silicon filmfor LP 120 and the hard mask layer 110 at the same time. It ispreferable that the concentration of P is in the range of 2 wt % to 5 wt%. In the 1^(st) polishing process, for example, it is possible that thepressure applied to the Main brain/Retain ring/Inner tube (M/R/I) of CMPequipment is in the range of 2 to 8 psi (pound/in²), and P/H's rotationpower of CMP equipment is in the range of 30 to 150 rpm. As a result, LP122 is formed between word lines of the LPC region through the 2^(nd)polishing process.

[0021] According to the present invention, it is possible to polishevenly and separate the adjacent word lines stably by performing theflattening process using slurry with a doping material added at the timeof polishing process.

[0022] Moreover, according to the present invention, it is possible toprevent the short from taking place by securing stably the polishingprocess for forming a landing plug stably and improving the marginalityof space when forming storage nodes or bit line self align contacts,wherein the short otherwise could be generated between the storage nodesor bit line self align contacts and word lines.

[0023] Although the foregoing description has been made with referenceto the preferred embodiments, it is to be understood that changes andmodifications of the present invention may be made by the ordinaryskilled in the art without departing from the spirit and scope of thepresent invention and appended claims.

What is claimed is:
 1. A method for manufacturing a semiconductor devicecomprising the steps of: preparing a semiconductor substrate defined asan active region and a field region; forming a number of word lines inthe active region and the field region of the semiconductor substrate;depositing an insulator film over the upper part of a structure toinsulate word lines; patterning the insulator film to open word lines ofthe active region whereby forming a landing plug contact; depositing apoly silicon film to fill up the landing plug contact; performing afirst polishing process using slurry including a first doping materialand flattening the poly silicon film only, whereby exposing theinsulator film; and forming a landing plug by performing a secondpolishing process using slurry including a second doping material and byflattening all the upper part of the structure.
 2. The method of claim1, wherein the first doping material is boron.
 3. The method of claim 2,wherein the concentration of boron is in the range of 2 wt % to 5 wt %.4. The method of claim 1, wherein the second doping material isphosphorus.
 5. The method of claim 4, wherein the concentration ofphosphorus is in the range of 2 wt % to 5 wt %.